The present invention relates generally to transistor technology, and more specifically to controlling voltage of a stacked power clamp.
When an excess of electric charge, which is stored on an electrically insulated structure, electrostatic discharge (ESD) is a momentary and sudden electric current that finds a path to another structure at a different electrical potential. ESD events may lead to irreparable damage to an integrated circuit (IC). A clamping circuit structure, such as a RC clamp, are incorporated into the IC in order to protect against ESD. More specifically, the RC clamp provides ESD protection to the terminals which receive an operating voltage for driving an IC chip, or portions thereof. The RC clamp ensures that a sudden surge in voltage from an ESD event can be safely discharged without damaging the IC. The RC clamp, while holding the voltage across the power supply terminals to the power supply voltage, requires one or more relatively large field-effect transistors, or “BigFETs,” capable of discharging the electrical current produced from an ESD event.